1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device which operates in synchronous with an external clock signal.
2. Description of Related Art
Recently, in order to cope with the speeding-up of a CPU, a dynamic random access memory (DRAM) which operates in synchronous with an external system clock signal, i.e., a synchronous DRAM (called "SDRAM") has been developed and manufactured. In the SDRAM, an address and a command which are supplied to pins of the semiconductor memory device are latched at the rising edge of the external clock signal (CLK). Moreover, the internal operation is executed in synchronous with the external clock signal (CLK).
Briefly describing the operation of the SDRAM in comparison with a general-purpose asynchronous DRAM, the case that an active command is given to the SDRAM at a rising edge of the external clock signal is equivalent to the case that a row address strobe (RAS-) ("-" shows an inverted signal and means that the signal is low active) is changed from an "H" level (high level) to a low level (low level) in the general-purpose asynchronous DRAM. That is, in response to an active command, one of word lines corresponding to a row address applied to the address input pins is selected. On the contrary, the case that a precharge command is given at the rising edge of the external clock signal is equivalent to the case that the row address strobe RAS- signal is changed from the "L" level to the "H" level in the general-purpose asynchronous DRAM. As a result, a data value is restored in a memory cell, the selected word line is set to a non-selected state, and nodes in respective portions are precharged.
Also, in the SDRAM, programming can be externally made so that the SDRAM can operate under the optimal condition with the system clock signal having a predetermined frequency. This can be achieved by giving an address key to the address simultaneously with a mode register set command. As one of the operation modes of the SDRAM, a column address strobe (CAS) latency is important. The CAS latency is defined as the number of clock cycles from the time when a read command is issued to the time when the first data is outputted and latched. Also, the continuous read or write operation is called a "burst". The burst length can be also set in the mode setting.
In a case of the burst mode in the SDRAM, addresses do not have to be continuously inputted from outside. Internal addresses (column addresses) are automatically generated by an internal counter using the first column address as a start address. There are two kinds of address generating methods. One is a "sequential type" of address generation and the other is an "interleave type" of address generation.
In the sequential type of address generation, the generated address data is incremented one by one in the lower bits of the generated address corresponding to the burst length. That is, assuming that the two lower bits of the start address are "0", "1", "2" and "3",in a case where the burst length is "4" for example, the internal addresses are changed so as to be "0".fwdarw."1".fwdarw."2".fwdarw."3", "1".fwdarw."2".fwdarw."3".fwdarw."0", "2".fwdarw."3".fwdarw."0".fwdarw."1" and "3".fwdarw."0".fwdarw."1".fwdarw."2", respectively. Here, the "change of the lower two bits" means that upper bits are not changed. That is, if the start address is 1A2 (Hex; hexadecimal notation), the internal address is changed to be 1A2(Hex).fwdarw.1A3(Hex).fwdarw.1A0(Hex).fwdarw.1A1(Hex).
On the other hand, in the "interleave type" of address generation, assuming that the two lower bits of the start address are "0", "1", "2" and "3", in a case where the burst length is "4" and a predetermined data is "1", for example, the internal addresses are changed so as to be "0".fwdarw."1".fwdarw."2".fwdarw."3", "1".fwdarw."2".fwdarw."3".fwdarw."0", "2".fwdarw."3".fwdarw."0".fwdarw."1" and "3".fwdarw."0".fwdarw."1".fwdarw."2", respectively.
When the read or write operation is executed for the burst length, the read or write operation is thereafter performed in the inside of the SDRAM.
FIGS. 1 and 2 are diagrams which show the structure of internal column address generating circuits of a column address buffer circuit in the conventional SDRAM having the burst function. FIG. 3 is a diagram which shows the structure of a generating circuit of a control signal YAL in the above conventional SDRAM. See Japanese Laid Open Patent Disclosure (Heisei 6-290582) as such a conventional example of SDRAM, for example. In the above reference, the changing operation of the internal address in the burst mode is performed only by the column address buffer circuit. Also, a counter of the address generating circuit is used commonly in both of the sequential mode and the interleave mode. Further, the counter is also used as a counter of a burst end detecting circuit. As a result, the high-speed operation in the burst mode of the conventional SDRAM is achieved.
Next, the conventional SDRAM will be described with reference to FIGS. 1 to 3. In FIGS. 1 to 3, reference symbols INV149 to INV194 denote inverters, NOR102 to NOR105 denote NOR gate circuits, NA109 to NA113 denote NAND gate circuits, and XOR104 to XOR106 denote exclusive logic summation (exclusive OR) gate circuits. Reference symbols TG115 to TG130 denote CMOS-type transfer gates each being composed of an N-channel MOS transistor and a P-channel MOS transistor (which is surrounded by a circle), and N153 to N207 denote nodes. Also, a signal MDBT specifies the sequential mode of the internal address when being in the "L" level and the interleave mode of the internal address when being in the "H" level. A signal RWCMD is a command signal which specifies the read operation or the write operation. A signal YAL is a signal which is used to latch an external address in the first cycle of the burst operation. IA0, IA1 are signals which shows the bit 0, i.e., LSB and bit 1 of the latched external address signal, respectively. A signal ICLK is an internal clock signal which is generated in response to the external clock signal CLK. The internal clock signal ICLK is generated as a 1-shot pulse in synchronous with the rising edge of the external clock signal. A signal PEN is an internal operation permission signal (a burst operation permission signal). Signals Y0T/Y0N and Y1T/Y1N (the signals Y0N and Y1N are inverted signals of the signals Y0T and Y1T) show two lower bits of the internal address signal from the LSB. Signals BCIN0 and BCIN1 indicate counter increment signals.
FIG. 1 shows the internal column address generating circuit of the column address buffer circuit for the LSB Y0 of the internal address signal and FIG. 2 shows the internal column address generating circuit for the second lower bit Y1 of the internal address signal for the LSB. The counter increment signal BCINO of FIG. 1 is inputted to the column address generating circuit of FIG. 2.
The column address generating circuit for the LSB Y0 of the internal address signal will be described with reference to FIG. 1. The external address signal IA0 is connected to terminals of the internal address signals Y0T and Y0N through the transfer gate TG115 which is controlled by the signal YAL and through the transfer gate TG116 which is controlled by the read/write command signal RWCMD, via the inverter INV154 and INV155 and the inverter INV154, INV158 and INV159, respectively. The output (the node N163) of the transfer gate TG115 is supplied to the first flip-flop composed of the inverters INV156 and INV157. The output (the node N163) of the transfer gate TG115 is also supplied to the second flip-flop composed of the inverters INV162 and INV163 through the NAND gate circuit NA109, the transfer gate TG117 controlled by the signal RWCMD, and the transfer gate TG118 controlled by the internal clock signal ICLK and the permission signal PEN. The output of the inverter INV162 constituting the second flip-flop is supplied through the transmission gate TG119 to one (the node N174) of the input terminals of exclusive OR gate circuit XOR104. The output (node N167) of the inverter INV156 constituting the first flip-flop is supplied to the other input terminal of the exclusive OR gate circuit XOR104. The output of the exclusive OR gate circuit XOR104 is connected to the internal address signal terminals Y0T/Y0N via the inverters INV154, INV155, INV158 AND INV159 through the transfer gate TG120 controlled by the signals RWCMD and MDBT. The output (the node N174) of the transfer gate TG119 is also supplied to the third flip-flop composed of the inverters INV164 and INV165. The output of the inverter INV164 is connected to the internal address signal terminals Y0T/Y0N via the inverters INV154, INV155, INV158 and INV159 to and so on through the transfer gate TG121 controlled by the signals MDBT and RWCMD. The output (the node N171) of the transfer gate TG117 is connected to the terminal of the signal BCIN0 via the inverter INV169. The output of the inverter INV165 constituting the third flip-flop is connected to the node N171 through the transfer gate TG122 controlled by the signal RWCMD.
Referring to FIG. 2, the structure of the column address generating circuit for the second lower bit Y1 of the address signal from the LSB will be described. In FIG. 2, the output of the transfer gate TG125 which corresponds to the transfer gate TG117 of FIG. 1 is not inputted to not the transfer gate TG126 which corresponds to the transfer gate TG118 of FIG. 1, but rather is inputted to one of the input terminals of the exclusive OR gate XOR105. The counter increment signal BCIN0 from the column address buffer circuit for the LSB Y0T of the internal address signal is supplied to the other input terminal of the exclusive OR gate XOR105. The output of the exclusive OR gate XOR105 is supplied to the transfer gate TG126 (corresponding to the transfer gate TG118 of FIG. 1) via the inverter INV181. The other sections of the structure of the column address buffer for the next lower bit Y1 of the address signal are the same as those for the LSB Y0 of the address signal shown in FIG. 1. Also, the counter increment signal BCIN1 is supplied to a column address buffer circuit (not illustrated) for the third lower bit Y2 of the address signal when the burst length is "8", for example.
Referring to FIG. 3, the address latch control signal YAL is generated based on the logic product of the signal by delaying the internal clock signal ICLK by the inverters INV192 and INV193 and the read/write command signal RWCMD.
Next, the operation of the conventional internal address generating circuit will be described with reference to the timing charts of FIGS. 4A to 4M. For simple description, assume that the CAS latency (CLT) is "3" and the burst length (BL) is "4".
First, the operation of the conventional internal address generating circuit in the sequential mode will be described. In this case, the signal MDBT which controls the mode is present to the "L" level.
When a read or write command ("the read command" in FIG. 4A) is first latched, the signal RWCMD is set to the "H" level during a time period of the external clock, as shown in FIG. 4D. At that time, the 1-shot pulse of the internal clock signal ICLK is generated in synchronous with the external clock signal CLK, as shown in FIG. 4C, and the signal YAL is generated as a 1-shot pulse using the circuit shown in FIG. 3, as shown in FIG. 4F. Since the transfer gates TG115 and TG123 are turned on while the signal YAL is in the "H" level, the latched external address signals are taken in the SDRAM and the address signal bits IA0 and IA1 are latched by the first flip-flop composed of the inverter INV156 and INV157 and the first flip-flop composed of the inverters INV175 and INV176, respectively. At this time, the read/write command signal RWCMD is in the "H" level so that the transfer gates TG116 and TG124 are in the ON condition. As a result, the latched external address bit signals IA0 and IA1 are output to the internal address signal terminals Y0T/Y0N and Y1T/Y1N just as they are (The start address is "0"), as shown in FIGS. 4H and 4I.
On the other hand, when the signal RWCMD is in the "H" level as shown in FIG. 4D, since the transfer gates TG117 and TG125 are in the ON state, the information of the start address, i.e., the latched address bit signals, are transferred to the nodes N171 and N195. In this case, because the external address bit signals IA0 and IA1 are both in the "L" level as shown in FIG. 4B, the potentials of the nodes N171 and N195 as the outputs of the transfer gates TG117 and TG125 for transferring the output of the NAND gates NA109 and NA111 are set to the "H" level, respectively. As a result, the counter increment signals BCIN0 and BCIN1 are set to the "L" level as shown in FIGS. 4J and 4K.
When in response to the next pulse of the external clock signal, the read/write RWCMD control signal is changed from the "H" level to the "L" level as shown in FIG. 4D, the transfer gate TG116 is turned off in the column address generating circuit shown in FIG. 1, because the signal MDBT is fixed on the "L" level. On the contrary, the transfer gate TG121 is turned on. In the column address generating circuit shown in FIG. 2, the transfer gate TG124 is turned off and the transfer gate TG129 is turned on. Also, the transfer gates TG120 and TG128 are held in the OFF state in this case. However, the transfer gates TG119 and TG127 are set to the ON state in response to the 1-shot pulse of the internal clock ICLK before the transfer gates TG121 and TG129 are set to the ON state. As a result, an address bit signal obtained by adding "1" to the LSB of the latched start external address signal is transferred to the nodes N175 and N202 which are the outputs of the inverters INV164 and INV187 constituting the third flip-flops, respectively. That is, in this case, the voltage of the node N175 of FIG. 1 changes from the "L" level to the "H" level. In FIG. 2, since the inputted counter increment signal BCIN0 is in the "L" level and the voltage of the node N195 which is the output terminal of the transfer gate TG125 is in the "H" level, the output of the exclusive OR gate circuit XOR105 is set to the "H" level. As a result, the node N202 is held in the "L" level through the inverters INV181, INV185 and INV187. Therefore, when the transfer gates TG121 and TG129 are set to the ON state, the LSB Y0T of the internal address signal changes from the "L" level to the "H" level as shown in FIG. 4H. On the other hand, the next lower bit Y1T of the internal address signal is held in the "L" level as shown in FIG. 4I. That is, in this manner, the lower bits of the internal address signal are updated by "1" from "0" of the start address to "1".
Moreover, in response to the following clock cycle, the internal address signals obtained by further adding "1" are supplied to the nodes N175 and N202 in response to the internal clock signal ICLK. The supplied internal address signals are transferred to the internal address signal terminals Y0T/Y0N and Y1T/Y1N through the transfer gates TG121 and TG129, as shown in FIGS. 4H and 4I, respectively. That is, the LSB of the internal address signal Y0T is changed from the "H" level to the "L" level. On the other hand, the next lower bit Y1T of the internal address signal is changed from the "L" level to the "H" level. As a result, the lower bits of the internal address (the column address) changes from "1" to "2".
Further, similarly, in the following clock cycle, the internal address is added with "1" from the previous internal address in response to the 1-shot pulse of the internal clock signal ICLK, so that the LSB Y0T of the internal address is changed from the "L" level to the "H" level as shown in FIG. 4H. On the other hand, the next lower bit Y1T of the internal address is held in the "H" level as shown in FIG. 4I. As a result of the lower bits of the internal address changes from "2" to "3".
As described above, in a case where the start address is "0" and the burst length is "4" in the sequential mode, it would be understood that the internal address is incremented in the manner of "0".fwdarw."1".fwdarw."2".fwdarw."3".
Also, while the column selection line signal (CSL) is in the active state, i.e., during the high level period of the signal CSL, access to memory cells having a column address defined by the internal address, i.e., a read or write operation from or to the memory cells is performed, as shown in FIG. 4L. The read operation is shown in FIGS. 4A to 4M. Because the CAS latency is "3", data output DOUT is started at the rising timing of the third clock pulse from the first clock pulse, in response to which the read command has been latched, as shown in FIG. 4M.
Next, in the interleave mode, the mode signal MDBT is present to the "H" level. When a read or write command is inputted, in the first clock cycle, the external address is output just as it is, in the same manner as in the sequential mode. On the other hand, when the inverted signal of the signal MDBT is inputted to one of the input terminals of each of the NAND gate circuits NA109 and NA111, the outputs of the NAND gate circuits NA109 and NA111 are always set to the "H" level, because the signal MDBT is present to the "H" level. The voltage levels of the nodes N171 and N195 which are connected with the outputs of the NAND gate circuits NA109 and NA111 through the transfer gates TG117 and TG125 are set to the "H" level irrespective of the start address. Also, the counter increment signals BCIN0 and BCIN1 are both set to the "L" level.
In the next clock cycle, the transfer gates TG119 and TG127 are turned on in response to 1-shot pulse of the internal clock signal ICLK in the same manner as in the sequential mode. As a result, the node N174 is changed from the "H" level to the "L" level and the node N201 is held to the "H" level. On the other hand, the signal MDBT is present to the "H" level, so that the transfer gates TG120 and TG128 are both turned on. Therefore, in FIG. 1, the result of calculation of the exclusive logic summation of the signals on the nodes N167 and N174 by the exclusive OR gate XOR104 is outputted to the internal address signal terminal Y0T/Y0N. Also, in FIG. 2, the result of calculation of the exclusive logic summation of the signals in the nodes N191 and N201 by the exclusive OR gate XOR106 is outputted to the internal address signal terminal Y1T/Y1N. This operation is logically the same as that the result of the exclusive logic summation calculation of the external address signal bit latched in the first clock cycle and a first data which is always "1" in the sequential mode and a predetermined data in the interleave mode, is outputted as the internal address signal bit.
In the next clock cycle, the first data is further added and as a result of this the result of calculation of the exclusive logic summation of the latched first external address and a second data equal to the twice of the first data is outputted as the internal address signal.
Further, in the next clock cycle, the result of calculation of the exclusive logic summation of the latched first external address and a third data equal to the three times of the first data is outputted as the internal address signal.
In this way, in a case that the burst length is "4" in the interleave mode, when the start address is "0", it could be seen that the internal address advances to be "0".fwdarw."1".fwdarw."2".fwdarw."3".
As described above, in the above conventional example, the internal address can be generated in the column address buffer circuit in the burst operation of the read or write operation. Also, the description when the burst length (BL) is "4" was given. However, using the same column address buffer circuit, the internal addresses can also be generated when the burst (BL) length is "2" or "8" or a full page.
In the above conventional semiconductor memory device, the paths of the internal address signals to be generated are as follows. In the first clock cycle, the 1-shot pulse internal clock signal ICLK is generated in response to the external clock signal CLK, the signal YAL is generated in response to the 1-shot pulse internal clock signal ICLK, the internal address bit signals Y0T/Y0N are generated from the latched external address IA0 and then the internal address bit signal Y1T/Y1N are generated. In the second clock cycle, the 1-shot pulse internal clock signal ICLK is generated in response to the external clock signal CLK, the signal RWCMD is reset in response to the 1-shot internal clock signal ICLK, the internal address bit signals Y0T/Y0N are generated from the latched external address IA0 in response to the resetting of the signal RWCMD, and then the internal address bit signals are generated. In the third clock cycle, the 1-shot pulse internal clock signal ICLK is generated in response to the external clock signal CLK, the counter is incremented in response to the 1-shot internal clock signal ICLK, the internal address bit signals Y0T/Y0N are generated from the latched external address IA0, and then the internal address bit signals are generated. The subsequent internal address bit signals are generated in the same manner as in the third clock cycle. In this manner, in the conventional column address buffer circuit, the paths through which the address signals pass when the internal address signals are generated in response the internal clock signal ICLK are different from each other. Therefore, there is a problem in that it is difficult to adjust the time period from the rising edge of the external clock signal to appearance of the internal address signal. That is, unless the time period required to generate the internal address signal is constant, the "H" level duration time periods of the signal CSL, i.e., the access permission time periods to the memory cells, vary. Therefore, in a case where the time period of the external clock signal CLK is shortened, i.e., the operation frequency is increased, there is a problem in that the maximum frequency is determined based on the shortest "H" level duration time period of the signal CSL. This is because the memory cells having a selected column address need to be accessed during the "H" level time period of the signal CSL. For this reason, the time period of the internal clock signal ICLK is determined based on the shortest time period of the "H" level time periods of the signal CSL.